@PeterCxy I didn't check at all, but I have to say that someone MUST have already written a VHDL/Verilog to redstone compiler or synthesizer.

@niconiconi I might have seen one too but it generates very sub-optimal circuits and is quite useless for anything large.

@PeterCxy Agree, a fully functional EDA would be great. Perhaps we also need bounded model checking and formal verification tools for redstone 🤣

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